Advances in CMOS technology have resulted in high-performance and low-cost consumer electronics. One of the main driving forces in this progress is technology scaling. The development of integrated circuits is continuously moving to a system-on-chip realization. where the digital signal processing is integrated with analog and mixed-signal circuits. Designing a system-on-chip, architecture choice is important. Another issue is the high-performance analog-to-digital converter, which is often a bottleneck in the system-on-chip design.
An overview of the analog-to-digital conversion performance roadmap and possible applications is given in this licentiate thesis. A high-speed track-and-hold circuit is analyzed as a critical block in the analog-to-digital converter. The main sampling circuit nonidealities and limiting factors are formulated. Several solutions to improve the track-and-hold circuit performance are proposed. To verify the proposed ideas, test chips in 0.35-μm CMOS technology are designed and fabricated. The basic measurement methods are discussed to characterize the high-speed track and-hold circuit performance.
As an application of the analog-to-digital conversion, different receiver architectures are described and compared. The homodyne and the direct analog-to-digital conversion receiver architectures are found to be the most suitable ones for system-on-chip implementation. A new receiver architecture, which utilizes direct sampling at RF, is proposed. An improved high-speed sampling circuit is used in this architecture together with time-interleaved analog-to-digital conversion. The GSM-1800 specification is chosen as target.
Different readout architectures for uncooled IR detection are also described in this thesis. First, an introduction to the infrared detection and readout principles is presented. Next, the readout architectures are compared, considering different degrees of parallelism. The design parameters are optirnized to have the lowest noise equivalent temperature difference (NETD) and the power consumption is chosen to be equal in all readout architectures. The pixelwise architecture is found to have the lowest NETD and the most reasonable design parameters when a realistic noise model is considered.
To summarize the main contributions of this thesis, they are as follows: comparison of readout architectures for uncooled IR detector arrays; a MOS switch linearization method for high-speed sampling is proposed; a sampling error minimization method by using a differential clock is described; a radio architecture with an RF sampling receiver is proposed.
Linköping: Linköping studies in science and technology , 2002. , 26 p.
2002-09-02, Sal Algoritmen, Linköpings universitet, Linköping, 10:15 (Swedish)