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Signal readout and sampling in CMOS
Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
2002 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

Advances in CMOS technology have resulted in high-performance and low-cost consumer electronics. One of the main driving forces in this progress is technology scaling. The development of integrated circuits is continuously moving to a system-on-chip realization. where the digital signal processing is integrated with analog and mixed-signal circuits. Designing a system-on-chip, architecture choice is important. Another issue is the high-performance analog-to-digital converter, which is often a bottleneck in the system-on-chip design.

An overview of the analog-to-digital conversion performance roadmap and possible applications is given in this licentiate thesis. A high-speed track-and-hold circuit is analyzed as a critical block in the analog-to-digital converter. The main sampling circuit nonidealities and limiting factors are formulated. Several solutions to improve the track-and-hold circuit performance are proposed. To verify the proposed ideas, test chips in 0.35-μm CMOS technology are designed and fabricated. The basic measurement methods are discussed to characterize the high-speed track and-hold circuit performance.

As an application of the analog-to-digital conversion, different receiver architectures are described and compared. The homodyne and the direct analog-to-digital conversion receiver architectures are found to be the most suitable ones for system-on-chip implementation. A new receiver architecture, which utilizes direct sampling at RF, is proposed. An improved high-speed sampling circuit is used in this architecture together with time-interleaved analog-to-digital conversion. The GSM-1800 specification is chosen as target.

Different readout architectures for uncooled IR detection are also described in this thesis. First, an introduction to the infrared detection and readout principles is presented. Next, the readout architectures are compared, considering different degrees of parallelism. The design parameters are optirnized to have the lowest noise equivalent temperature difference (NETD) and the power consumption is chosen to be equal in all readout architectures. The pixelwise architecture is found to have the lowest NETD and the most reasonable design parameters when a realistic noise model is considered.

To summarize the main contributions of this thesis, they are as follows: comparison of readout architectures for uncooled IR detector arrays; a MOS switch linearization method for high-speed sampling is proposed; a sampling error minimization method by using a differential clock is described; a radio architecture with an RF sampling receiver is proposed.

Place, publisher, year, edition, pages
Linköping: Linköping studies in science and technology , 2002. , 26 p.
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 967
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-34862Local ID: 23739OAI: oai:DiVA.org:liu-34862DiVA: diva2:255710
Presentation
2002-09-02, Sal Algoritmen, Linköpings universitet, Linköping, 10:15 (Swedish)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2017-12-14
List of papers
1. Readout architectures for uncooled IR detector arrays
Open this publication in new window or tab >>Readout architectures for uncooled IR detector arrays
2000 (English)In: Sensors and Actuators A-Physical, ISSN 0924-4247, E-ISSN 1873-3069, Vol. 84, no 3, 220-229 p.Article in journal (Refereed) Published
Abstract [en]

The main idea of this paper is to compare the readout architectures for uncooled microbolometer focal plane detector arrays with respect to the detector and readout circuit noise. The comparison is done keeping the total power consumption of all architectures constant. Three CMOS readout architectures with different degree of parallelism are described in this paper: pixelwise, columnwise and serial. The noise model of the readout circuit is given. Also, the optimization for the lowest NETD (noise equivalent temperature difference) and estimation of the self-heating effect is presented.

National Category
Natural Sciences
Identifiers
urn:nbn:se:liu:diva-47597 (URN)10.1016/S0924-4247(00)00313-7 (DOI)000088801600005 ()
Available from: 2009-10-11 Created: 2009-10-11 Last updated: 2017-12-13
2. Sampling error minimization using a differential bootstrapped sampler
Open this publication in new window or tab >>Sampling error minimization using a differential bootstrapped sampler
2001 (English)In: Proceedings of the SSoCC'01, 2001Conference paper, Published paper (Other academic)
Abstract [en]

This paper presents a novel bootstrap technique implemented in a fully-differential sampler. The main sampling errors are discussed and the sampling time variation for the bootstrapped sampler is derived. The proposed bootstrap sampler is compared with an ordinary sampler to show an improvement in SFDR. A differential clock sampling is introduced to minimize the sampling error due to noise in clock and power supply. Simulation results show significant improvement in sampling accuracy.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-102672 (URN)
Conference
Swedish System-on-Chip Conference 2001, Arild, Sweden. 20-21/3 2001
Available from: 2013-12-18 Created: 2013-12-18 Last updated: 2013-12-18
3. A 1 GHz linearized CMOS track-and-hold circuit
Open this publication in new window or tab >>A 1 GHz linearized CMOS track-and-hold circuit
2002 (English)In: IEEE International Symposium on Circuits and Systems, 2002: ISCAS 2002, 2002, 577-580 p.Conference paper, Published paper (Refereed)
Abstract [en]

A simple solution for linearization of the MOS sampling switch is proposed. It improves the SFDR of a T/H circuit and is suitable for high-speed applications. Sampling at a constant gate-source voltage minimizes sampling errors due to variable MOS sampling switch ON-conductance and channel charge injection, and also eliminates input-dependent sampling instant variation. The proposed linearized T/H circuit is fabricated in a 0.35-μm CMOS process. Test measurements show the sampling of a 1 GHz signal.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-34846 (URN)23650 (Local ID)0-7803-7448-7 (ISBN)23650 (Archive number)23650 (OAI)
Conference
IEEE International Symposium on Circuits and Systems (ISCAS), Scottsdale, Arizona, 26-29 May 2002
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2013-12-18
4. An RF sampling front-end for a digital receiver
Open this publication in new window or tab >>An RF sampling front-end for a digital receiver
2002 (English)In: Proceedings of the 20th IEEE NORCHIP Conference, Copenhagen: TechnoData A/S , 2002, 21-26 p.Conference paper, Published paper (Refereed)
Abstract [en]

An RF sampling front-end is presented in this paper. The front-end specifications are defined using the GSM-1800 requirements. The implementation of the front-end has been concentrated on a sampler, which is expected to be the most critical block. A linearized sampler is proposed to achieve the high linearity specifications. The sampler enables sampling of a wide band signal at high frequencies. lt is designed in 0.35-μm CMOS process. The simulation results proves, that the sampler achieves high linearity up to carrier frequency. To clock the linearized sampler a low-jitter clock path is presented. lt reduces the clock path sensitivity to power supply variations and protects the clock from additional on-chip jitter.

Place, publisher, year, edition, pages
Copenhagen: TechnoData A/S, 2002
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-34847 (URN)23651 (Local ID)23651 (Archive number)23651 (OAI)
Conference
20th IEEE NORCHIP Conference, Copenhagen, Denmark, November 11-12, 2002
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2013-12-18

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