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Differential charge transfer sense ampliifier
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
Intel Corp., USA.
Intel Corp., USA.
2004 (English)Patent (Other (popular science, discussion, etc.))
Abstract [en]

A sense amplifier for reading memory cells in a SRAM, the sense amplifier comprising two gate-biased pMOSFETs, each corresponding to a selected bitline. The gates of the two gate-biased pMOSFETs have their gates biased to a bias voltage, their sources coupled to the selected bitlines via column-select transistors, and their drains coupled via pass transistors to the two ports of two cross-coupled inverters, the cross-coupled inverters forming a latch. After a selected bitline pair has been pre-charged and the pre-charge phase ends, one of the two gate-biased pMOSFETs quickly goes into its subthreshold region as one of the bitlines discharges through its corresponding memory cell, thereby cutting off the bitline's capacitance from the sense amplifier. When the pass transistors are enabled, the other of the two pMOSFETs allows a significant bitline charge to transfer via its corresponding pass transistor to its corresponding port, whereas a relatively much smaller charge is transferred to the other port. This charge transfer scheme allows a differential voltage to quickly develop at the ports, thereby providing a fast latch and read operation with reduced power consumption. Bitline voltage swing may also be reduced to reduce power consumption.

Place, publisher, year, edition, pages
2004.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-34870Local ID: 23756OAI: oai:DiVA.org:liu-34870DiVA: diva2:255718
Patent
US US 6751141 B1 (2004-06-15)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2017-01-19Bibliographically approved

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Alvandpour, Atila

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