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Current leakage reduction for loaded bit-lines in on-chip memory structures
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
Inten Corp., USA.
Inten Corp., USA.
2003 (English)Patent (Other (popular science, discussion, etc.))
Abstract [en]

Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

Place, publisher, year, edition, pages
2003.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-34886Local ID: 23791OAI: oai:DiVA.org:liu-34886DiVA: diva2:255734
Patent
US US 6519178 B2 (2003-02-11)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2017-01-19Bibliographically approved

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Alvandpour, Atila

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