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Self-tested self-synchronization circuit for mesochronous clocking
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
2001 (English)In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 48, no 2, 129-140 p.Article in journal (Refereed) Published
Abstract [en]

In large-scale and high-speed systems, global synchronization has been commonly used to protect clocked I/O from data read failure caused by metastability. There are many drawbacks with global synchronization, which will approach its physical limit in the future as system clock frequency and system scale increase simultaneously. Mesochronous clocking overcomes these drawbacks, but without a proper delay or phase control, a metastability problem occurs. Self-tested self-synchronization (STSS) was proposed to solve this problem. In this paper, we describe two STSS methods, STSS-1 and STSS-2, implemented by two-phase input ports for parallel/serial data transfer. Measurements on a test chip for the two methods show that a data rate of 750 Mb/s is reached with 3.6-V power supply in 0.6-╡m CMOS. Comparison is made between STSS-1 and STSS-2.

Place, publisher, year, edition, pages
2001. Vol. 48, no 2, 129-140 p.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-34953DOI: 10.1109/82.917781Local ID: 24285OAI: oai:DiVA.org:liu-34953DiVA: diva2:255801
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2017-12-13

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Svensson, Christer

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