Modeling of dynamic errors in algorithmic A/D converters
2001 (English)In: The 2001 IEEE International Symposium on Circuits and Systems, 2001. ISCAS 2001., Piscataway: IEEE , 2001, 455-458 p.Conference paper (Refereed)
In communication applications, the requirements on A/D converters are high and increasing. To be able to design high-perfomance converters, it is important to understand the speed limitations. In this work, performance decrease caused by dynamic errors related to settling time of the switched circuits at high sampling frequencies is investigated
Place, publisher, year, edition, pages
Piscataway: IEEE , 2001. 455-458 p.
National CategoryEngineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-34965DOI: 10.1109/ISCAS.2001.922083Local ID: 24312ISBN: 0-7803-6685-9OAI: oai:DiVA.org:liu-34965DiVA: diva2:255813
The 2001 IEEE International Symposium on Circuits and Systems, 2001. ISCAS 2001. Sydney, Australia. 6-9 May 2001.