A regular parallel multiplier which utilizes multiple carry-propagate adders.
2001 (English)In: IEEE International Symposium on Circuits and Systems ISCAS.,2001, Piscataway: IEEE , 2001, Vol. 4, 166-169 p.Conference paper (Refereed)
A new regular partial-product reduction tree for parallel multipliers is presented in this paper. The reduction tree has a simple and efficient interconnect configuration and a minimal hardware usage. The reduction tree has a gate structure, which allows for extensive use of carry-propagation adders. Since carry-propagation adders can be very efficiently implemented, significant delay reduction is expected for large multipliers
Place, publisher, year, edition, pages
Piscataway: IEEE , 2001. Vol. 4, 166-169 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-34972DOI: 10.1109/ISCAS.2001.922198Local ID: 24326ISBN: 0-7803-6685-9OAI: oai:DiVA.org:liu-34972DiVA: diva2:255820
2001 IEEE International Symposium on Circuits and Systems, 6-9 May 2001, Sydney, NSW, Australia