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A regular parallel multiplier which utilizes multiple carry-propagate adders.
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
Chalmers.
2001 (English)In: IEEE International Symposium on Circuits and Systems ISCAS.,2001, Piscataway: IEEE , 2001, Vol. 4, 166-169 p.Conference paper, Published paper (Refereed)
Abstract [en]

A new regular partial-product reduction tree for parallel multipliers is presented in this paper. The reduction tree has a simple and efficient interconnect configuration and a minimal hardware usage. The reduction tree has a gate structure, which allows for extensive use of carry-propagation adders. Since carry-propagation adders can be very efficiently implemented, significant delay reduction is expected for large multipliers

Place, publisher, year, edition, pages
Piscataway: IEEE , 2001. Vol. 4, 166-169 p.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-34972DOI: 10.1109/ISCAS.2001.922198Local ID: 24326ISBN: 0-7803-6685-9 (print)OAI: oai:DiVA.org:liu-34972DiVA: diva2:255820
Conference
2001 IEEE International Symposium on Circuits and Systems, 6-9 May 2001, Sydney, NSW, Australia
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2015-04-17

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Eriksson, Henrik

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  • apa
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