liu.seSearch for publications in DiVA
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
School of Electronics and Computer Science University of Southampton.
Show others and affiliations
2006 (English)In: International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'06), Arlington, Virginia, USA, October 4-6, 2006., Arlington: IEEE Computer Society Press , 2006, 477-485 p.Conference paper, Published paper (Refereed)
Abstract [en]

High temperature has become a major problem for system-on-chip testing. In order to reduce the test time while keeping the temperature of the chip under test within a safe range, a thermal-aware test scheduling technique is required. This paper presents an approach to minimize the test time and, at the same time, prevent the temperature of cores under test going over the given upper limit. We employ test set partitioning to divide test sets into shorter test sequences, and add cooling spans between test sequences, so that overheating can be avoided. Moreover, test sequences from different test sets are interleaved, in order to utilize the cooling spans and the test bus bandwidth for test data transportation, hence the total test time is reduced. The test scheduling problem is formulated as a combinatorial optimization problem, and we use constraint logic programming to solve it in order to obtain the optimal solution. Experimental results have shown the efficiency of the proposed approach.

Place, publisher, year, edition, pages
Arlington: IEEE Computer Society Press , 2006. 477-485 p.
Keyword [en]
testing, scheduling, termal-aware, overheating
National Category
Computer Science
Identifiers
URN: urn:nbn:se:liu:diva-35460DOI: 10.1109/DFT.2006.65Local ID: 26913ISBN: 0-7695-2706-X (print)OAI: oai:DiVA.org:liu-35460DiVA: diva2:256308
Conference
International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'06), Arlington, Virginia, USA, October 4-6, 2006.
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2013-08-16

Open Access in DiVA

No full text

Other links

Publisher's full texthttp://www.ida.liu.se/labs/eslab/publications/pap/db/zhihe_dft06.camera.pdf

Authority records BETA

He, ZhiyuanPeng, ZeboEles, Petru Ion

Search in DiVA

By author/editor
He, ZhiyuanPeng, ZeboEles, Petru Ion
By organisation
The Institute of TechnologyESLAB - Embedded Systems Laboratory
Computer Science

Search outside of DiVA

GoogleGoogle Scholar

doi
isbn
urn-nbn

Altmetric score

doi
isbn
urn-nbn
Total: 161 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf