Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
2006 (English)In: International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'06), Arlington, Virginia, USA, October 4-6, 2006., Arlington: IEEE Computer Society Press , 2006, 477-485 p.Conference paper (Refereed)
High temperature has become a major problem for system-on-chip testing. In order to reduce the test time while keeping the temperature of the chip under test within a safe range, a thermal-aware test scheduling technique is required. This paper presents an approach to minimize the test time and, at the same time, prevent the temperature of cores under test going over the given upper limit. We employ test set partitioning to divide test sets into shorter test sequences, and add cooling spans between test sequences, so that overheating can be avoided. Moreover, test sequences from different test sets are interleaved, in order to utilize the cooling spans and the test bus bandwidth for test data transportation, hence the total test time is reduced. The test scheduling problem is formulated as a combinatorial optimization problem, and we use constraint logic programming to solve it in order to obtain the optimal solution. Experimental results have shown the efficiency of the proposed approach.
Place, publisher, year, edition, pages
Arlington: IEEE Computer Society Press , 2006. 477-485 p.
testing, scheduling, termal-aware, overheating
IdentifiersURN: urn:nbn:se:liu:diva-35460DOI: 10.1109/DFT.2006.65Local ID: 26913ISBN: 0-7695-2706-XOAI: oai:DiVA.org:liu-35460DiVA: diva2:256308
International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'06), Arlington, Virginia, USA, October 4-6, 2006.