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Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
Dept. of Electrical and Computer Eng. Duke University.
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
2006 (English)In: International Test Conference,2006, Santa Clara: IEEE Computer Society Press , 2006, 32.1- p.Conference paper, Published paper (Refereed)
Abstract [en]

Concurrent testing of the cores in a modular core-based System-on-Chip reduces the test application time but increases the test power consumption. Power models and scheduling algorithms have been proposed to schedule the tests as concurrently as possible while respecting the power budget. The commonly used global peak power model, with a single value capturing the power dissipated by a core when tested, is pessimistic but simple for a scheduling algorithm to handle. In this paper, we propose a cycle-accurate power model with a power value per clock cycle and a corresponding scheduling algorithm. The model takes into account the switching activity in the scan chains caused by both the test stimuli and the test responses during scan-in, launch-and-capture, and scan-out. Further, we allow a unique power model per wrapper chain configuration as the activity in a core will be different depending on the number of wrapper chains at a core. Extensive experiments on ITC'02 benchmarks and an industrial design show that the testing time can be substantially reduced (on average 16.5% reduction) by using the proposed cycle-accurate test power model.

Place, publisher, year, edition, pages
Santa Clara: IEEE Computer Society Press , 2006. 32.1- p.
Keyword [en]
testing, system-on-chip, test scheduling, power modelling
National Category
Computer Sciences
Identifiers
URN: urn:nbn:se:liu:diva-35461DOI: 10.1109/TEST.2006.297693Local ID: 26914ISBN: 1-4244-0292-1 (print)ISBN: 1-4244-0292-1 (print)OAI: oai:DiVA.org:liu-35461DiVA: diva2:256309
Conference
International Test Conference,2006
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2018-01-13

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Publisher's full texthttp://www.ida.liu.se/labs/eslab/publications/pap/db/sohsa_itc06.camera.pdf

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Samii, SoheilLarsson, ErikPeng, Zebo

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Citation style
  • apa
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