Hybrid BIST Energy Minimisation Technique for System-on-Chip Testing
2006 (English)In: IEE Proceedings - Computers and digital Techniques, ISSN 1350-2387, E-ISSN 1359-7027, Vol. 153, no 4, 208-216 p.Article in journal (Refereed) Published
The energy minimisation problem for system-on-chip testing is addressed. A hybrid built-in self-test architecture is assumed where a combination of deterministic and pseudorandom test sequences are used. The objective of the proposed technique is to find the best ratio of these sequences so that the total energy is minimised and the memory requirements for the deterministic test set are met without sacrificing test quality. Unfortunately, exact algorithms for finding the best solutions to the above problem are computationally very expensive. Therefore, an estimation methodology for fast calculation of the hybrid test set and two different heuristic algorithms for energy minimisation were proposed. Experimental results have shown the efficiency of the proposed approach for finding reduced energy solutions with low computational overhead.
Place, publisher, year, edition, pages
2006. Vol. 153, no 4, 208-216 p.
testing, hybrid BIST, energy minimization, system-on-chip
IdentifiersURN: urn:nbn:se:liu:diva-35463DOI: 10.1049/ip-cdt:20050064Local ID: 26925OAI: oai:DiVA.org:liu-35463DiVA: diva2:256311