liu.seSearch for publications in DiVA
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Hybrid BIST Energy Minimisation Technique for System-on-Chip Testing
Dept. of Computer Engineering Tallinn University of Technology.
Dept. of Computer Engineering Tallinn University of Technology.
Dept. of Computer Engineering Tallinn University of Technology.
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
2006 (English)In: IEE Proceedings - Computers and digital Techniques, ISSN 1350-2387, E-ISSN 1359-7027, Vol. 153, no 4, 208-216 p.Article in journal (Refereed) Published
Abstract [en]

The energy minimisation problem for system-on-chip testing is addressed. A hybrid built-in self-test architecture is assumed where a combination of deterministic and pseudorandom test sequences are used. The objective of the proposed technique is to find the best ratio of these sequences so that the total energy is minimised and the memory requirements for the deterministic test set are met without sacrificing test quality. Unfortunately, exact algorithms for finding the best solutions to the above problem are computationally very expensive. Therefore, an estimation methodology for fast calculation of the hybrid test set and two different heuristic algorithms for energy minimisation were proposed. Experimental results have shown the efficiency of the proposed approach for finding reduced energy solutions with low computational overhead.

Place, publisher, year, edition, pages
2006. Vol. 153, no 4, 208-216 p.
Keyword [en]
testing, hybrid BIST, energy minimization, system-on-chip
National Category
Computer Science
Identifiers
URN: urn:nbn:se:liu:diva-35463DOI: 10.1049/ip-cdt:20050064Local ID: 26925OAI: oai:DiVA.org:liu-35463DiVA: diva2:256311
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2013-08-16

Open Access in DiVA

No full text

Other links

Publisher's full texthttp://www.ida.liu.se/labs/eslab/publications/pap/db/gerje_iee_cdt06.pdf

Authority records BETA

Peng, Zebo

Search in DiVA

By author/editor
Peng, Zebo
By organisation
The Institute of TechnologyESLAB - Embedded Systems Laboratory
In the same journal
IEE Proceedings - Computers and digital Techniques
Computer Science

Search outside of DiVA

GoogleGoogle Scholar

doi
urn-nbn

Altmetric score

doi
urn-nbn
Total: 105 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf