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Off-line Testing of Delay Faults in NoC Interconnects
Jönköping University, Sweden.
Tallinn University of Technology, Estonia.
Jönköping University, Sweden.
Tallinn University of Technology, Estonia.
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2006 (English)In: 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, 2006, IEEE Computer Society, 2006, 677-680 p.Conference paper, Published paper (Refereed)
Abstract [en]

Testing of high density SoCs operating at high clock speeds in an important but difficult problem. Many faults, like delay faults, in such sub-micron chips may only appear when the chip works at normal operating speed. In this paper, we propose a methodology for at-speed testing of delay faults in links connecting two distinct clock domains in a SoC. We give an analytical analysis about the efficiency of this method. We also propose a simple digital hardware structure for the receiver end of the link under test to detect delay faults. It is possible to extend our method to combine it with functional testing of the link and adapt it for on-line testing.

Place, publisher, year, edition, pages
IEEE Computer Society, 2006. 677-680 p.
Keyword [en]
networks-on-chip, testing, delay faults
National Category
Computer Science
Identifiers
URN: urn:nbn:se:liu:diva-35468DOI: 10.1109/DSD.2006.72ISI: 000242376400091Local ID: 26945ISBN: 0-7695-2609-8 (print)OAI: oai:DiVA.org:liu-35468DiVA: diva2:256316
Conference
9th EUROMICRO Conference on Digital System Design - Architectures, Methods and Tools (DSD 2006), 30 August-1 September 2006, Dubrovnik, Crotia
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2012-11-16

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Peng, Zebo

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CiteExportLink to record
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Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
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Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf