Mapping of Fault-Tolerant Applications with Transparency on Distributed Embedded Systems
2006 (English)In: 9th Euromicro Conference on Digital System Design,2006, Dubrovnik: IEEE Computer Society Press , 2006, 313- p.Conference paper (Refereed)
In this paper we present an approach for the mapping optimization of fault-tolerant embedded systems for safety-critical applications. Processes and messages are statically scheduled. Process re-execution is used for recovering from multiple transient faults. We call process recovery transparent if it does not affect operation of other processes. Transparent recovery has the advantage of fault containment, improved debugability and less memory needed to store the fault-tolerant schedules. However, it will introduce additional delays that can lead to violations of the timing constraints of the application. We propose an algorithm for the mapping of fault-tolerant applications with transparency. The algorithm decides a mapping of processes on computation nodes such that the application is schedulable and the transparency properties imposed by the designer are satisfied. The mapping algorithm is driven by a heuristic that is able to estimate the worst-case schedule length and indicate whether a certain mapping alternative is schedulable.
Place, publisher, year, edition, pages
Dubrovnik: IEEE Computer Society Press , 2006. 313- p.
embedded systems, real-time systems, fault tolerance, transient faults, design optimization, mapping, conditional scheduling
IdentifiersURN: urn:nbn:se:liu:diva-35469DOI: 10.1109/DSD.2006.65Local ID: 26946ISBN: 0-7695-2609-8OAI: oai:DiVA.org:liu-35469DiVA: diva2:256317
9th Euromicro Conference on Digital System Design,2006