An Architecture for Combined Test Data Compression and Abort-on-Fail Test
2007 (English)In: Asia and South Pacific Design Automation Conference,2007, Yokohama: IEEE Computer Society Press , 2007, 726- p.Conference paper (Refereed)
The low throughput at IC (Integrated Circuit) testing is mainly due to the increasing test data volume, which leads to high ATE (Automatic Test Equipment) memory requirements and long test application times. In contrast to previous approaches that address either test data compression or abort-on-fail testing, we propose an architecture for combined test data compression and abort-on-fail testing. The architecture improves throughput through multi-site testing as the ATE memory requirement is constant and independent of the degree of multi-site testing. For flexibility in modifying the test data at any time, we make use of a test program for decompression; only test independent evaluation logic is added to the IC. Major advantages compared to MISR (Multiple-Input Signature Register) based schemes are that our scheme (1) allows abort-on-fail testing at clock-cycle granularity, (2) does not impact diagnostic capabilities, and (3) needs no special care for the handling of unknowns (X).
Place, publisher, year, edition, pages
Yokohama: IEEE Computer Society Press , 2007. 726- p.
testing, electronic systems, test data compression, unknowns
National CategoryComputer Science
IdentifiersURN: urn:nbn:se:liu:diva-35471Local ID: 26948OAI: oai:DiVA.org:liu-35471DiVA: diva2:256319