A new simultaneous multislope ADC architecture for array implementations
2006 (English)In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 53, no 9, 921-925 p.Article in journal (Refereed) Published
This brief presents a new simultaneous multislope analog-digital converter (ADC) architecture suitable for array implementations in, e.g., CMOS image sensors (CISs). The simplest implementation is almost twice as fast as a conventional-slope ADC, while it requires only a small amount of extra circuitry. Measurements have been performed on a custom made CIS which implements parts of the proposed ADC. The measurements show good linearity and verify the concept of the new architecture
Place, publisher, year, edition, pages
2006. Vol. 53, no 9, 921-925 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-35616DOI: 10.1109/TCSII.2006.881817Local ID: 27966OAI: oai:DiVA.org:liu-35616DiVA: diva2:256464