6-bit flash ADC with dynamic element matching
2006 (English)In: Proc. IEEE 24th Norchip Conf., NORCHIP'06, 2006, , 159-162 p.159-162 p.Conference paper (Refereed)
Previous work have suggested approaches to introduce dynamic element matching (DEM) into the reference net of a flash analog-to-digital converter. No implementations of such circuits have however been reported. In this work the authors evaluate the suitability and estimate the performance enhancements of a recently proposed DEM architecture by using this in the design of a 6-bit Nyquist rate converter. The converter is sent for manufacturing in a 130 nm partially depleted silicon-on-insulator CMOS technology. It was simulated at transistor level in Cadence using the foundry provided BSIM3SOI Eldo models. These simulations yield a maximum sampling frequency of at least 350 MHz. The simulations also indicate a performance improvement in terms of spurious free dynamic range when using dynamic element matching.
Place, publisher, year, edition, pages
2006. , 159-162 p.159-162 p.
CMOS integrated circuits, analog-digital conversion, integrated circuit modeling, silicon-on-insulator
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-35796DOI: 10.1109/NORCHP.2006.329268Local ID: 28599ISBN: 1-4244-0772-9OAI: oai:DiVA.org:liu-35796DiVA: diva2:256644