Optimized Integration of Test Compression and Sharing for SOC Testing
2007 (English)In: Design, Automation, and Test in Europe Conference DATE07,2007, Nice, France: IEEE Computer Society Press , 2007, 207- p.Conference paper (Refereed)
The increasing test data volume needed to test core-based System-on-Chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requirements. TAT and ATE memory requirement can be reduced by test architecture design, test scheduling, sharing the same tests among several cores, and test data compression. We propose, in contrast to previous work that addresses one or few of the problems, an integrated framework with heuristics for sharing and compression and a Constraint Logic Programming technique for architecture design and test scheduling that minimizes the TAT without violating a given ATE memory constraint. The significance of our approach is demonstrated by experiments with ITC-02 benchmark designs.
Place, publisher, year, edition, pages
Nice, France: IEEE Computer Society Press , 2007. 207- p.
testing, system-on-chip, SOC, test scheduling, memory requirements, test data compression, constraint logic programming
IdentifiersURN: urn:nbn:se:liu:diva-35883DOI: 10.1109/DATE.2007.364592Local ID: 28907ISBN: 978-3-9810801-2-4OAI: oai:DiVA.org:liu-35883DiVA: diva2:256731
Design, Automation, and Test in Europe Conference DATE07,2007