Digit-serial/parallel multipliers with improved throughput and latency
2006 (English)In: Proc. 2006 IEEE Int. Symp. Circuits and Systems, ISCAS'06, 2006Conference paper (Refereed)
Digit-serial/parallel multipliers with improved throughput and latency are presented. The multipliers are based on unfolded bit-serial/parallel multipliers. The unfolding yields long critical paths that are reduced by splitting the multiplication as a sum of partial multiplications. Using a sum of two partial multiplications yields an increased throughput with between 50 and 120 percent and the latency is reduced with up to 50 percent, compared with the basic digit-serial/parallel multiplier based on unfolding.
Place, publisher, year, edition, pages
digital arithmetic, multiplying circuits
National CategoryOther Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-37343DOI: 10.1109/ISCAS.2006.1692507Local ID: 34725ISBN: 0-7803-9389-9OAI: oai:DiVA.org:liu-37343DiVA: diva2:258192