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Digit-serial/parallel multipliers with improved throughput and latency
Dept. of Tech., Univ. Kalmar.
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
2006 (English)In: Proc. 2006 IEEE Int. Symp. Circuits and Systems, ISCAS'06, 2006Conference paper, Published paper (Refereed)
Abstract [en]

Digit-serial/parallel multipliers with improved throughput and latency are presented. The multipliers are based on unfolded bit-serial/parallel multipliers. The unfolding yields long critical paths that are reduced by splitting the multiplication as a sum of partial multiplications. Using a sum of two partial multiplications yields an increased throughput with between 50 and 120 percent and the latency is reduced with up to 50 percent, compared with the basic digit-serial/parallel multiplier based on unfolding.

Place, publisher, year, edition, pages
2006.
Keyword [en]
digital arithmetic, multiplying circuits
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-37343DOI: 10.1109/ISCAS.2006.1692507Local ID: 34725ISBN: 0-7803-9389-9 (print)OAI: oai:DiVA.org:liu-37343DiVA: diva2:258192
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2009-10-14

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Vesterbacka, Mark

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CiteExportLink to record
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Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
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  • Other style
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Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf