Algorithm transformations in design of digit-serial FIR filters
2005 (English)In: IEEE Workshop Signal Processing Systems Design and Implementation, SIPS'05, 2005, , 81-86 p.81-86 p.Conference paper (Refereed)
Algorithm transformations for increased throughput and decreased power consumption in design of digit-serial FIR filters are discussed in this paper. Pipelining has been used for a long time for increasing the throughput of sequential algorithms. Here we introduce algorithm unfolding, which traditionally has been used in implementation of recursive algorithms, in a sequential FIR algorithm. Pipelining at algorithm and logic level, and algorithm unfolding are compared by HSPICE simulations of netlists extracted from layouts. For a given throughput requirement, the simulations show that algorithm unfolding without any pipelining is preferable for low power operation. Algorithm unfolding yields a decrease of the power consumption with 40, and 50 percent compared to pipelining at the logic or algorithm level, respectively. For minimum power consumption the digit-size should be tuned with the throughput requirement, i.e., using a large digit-size for low throughput requirement and decrease the digit-size with increasing throughput.
Place, publisher, year, edition, pages
2005. , 81-86 p.81-86 p.
FIR filters, SPICE, network synthesis, pipeline processing
National CategoryOther Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-37347DOI: 10.1109/SIPS.2005.1579843Local ID: 34786ISBN: 0-7803-9333-3OAI: oai:DiVA.org:liu-37347DiVA: diva2:258196