A kick-back reduced comparator for a 4-6-bit 3-GS/S flash ADC in a 90nm CMOS process
2007 (English)In: Proceedings of the 14th International Conference, Mixed Design of Integrated Circuits and Systems, Lodz, Poland: Technical university of Lodz , 2007, , 195-198 p.195-195 p.Conference paper (Refereed)
This paper presents a kick-back reduced comparator based on a senseamplifier type comparator. The kick-back charge and resulting voltage peak is reduced by 6x, which corresponds to a power reduction in the input driver and the resistance ladder of the same magnitude. A 4-6-bit 3-GS/s low-power flash ADC using the proposed comparator has been implemented in a 90nm CMOS process. The significantly lower requirements on input driver and resistance ladder have reduced the overall ADC power dissipation by 50%.
Place, publisher, year, edition, pages
Lodz, Poland: Technical university of Lodz , 2007. , 195-198 p.195-195 p.
comparator, kick-back, low-power, flash ADC, CMOS
National CategoryEngineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-38260DOI: 10.1109/MIXDES.2007.4286149Local ID: 43306ISBN: 83-922632-9-4OAI: oai:DiVA.org:liu-38260DiVA: diva2:259109
14th International Conference Mixed Design of Integrated Circuits and Systems, 21-23 June, Ciechocinek, Poland