Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip
2007 (English)In: 28th IEEE Real-Time Systems Symposium RTSS07,2007, Tucson, Arizona, USA: IEEE Computer Society Press , 2007, 49- p.Conference paper (Refereed)
In multiprocessor systems, the traffic on the bus does not solely originate from data transfers due to data dependencies between tasks, but is also affected by memory transfers as result of cache misses. This has a huge impact on worst-case execution time (WCET) analysis and, in general, on the predictability of real-time applications implemented on such systems. As opposed to the WCET analysis performed for a single processor system, where the cache miss penalty is considered constant, in a multiprocessor system each cache miss has a variable penalty, depending on the bus contention. This affects the tasks' WCET which, however, is needed in order to perform system scheduling. At the same time, the WCET depends on the system schedule due to the bus interference. In this paper we present an approach to worst-case execution time analysis and system scheduling for real-time applications implemented on multiprocessor SoC architectures. The emphasis of this paper is on the bus scheduling policy and its optimization, which is of huge importance for the performance of such a predictable multiprocessor application.
Place, publisher, year, edition, pages
Tucson, Arizona, USA: IEEE Computer Society Press , 2007. 49- p.
embedded systems, multiprocessor systems, memory transfers, bus scheduling, system-on-chip, worst-case execution time analysis, WCET
IdentifiersURN: urn:nbn:se:liu:diva-39294DOI: 10.1109/RTSS.2007.24Local ID: 47827ISBN: 978-0-7695-3062-8OAI: oai:DiVA.org:liu-39294DiVA: diva2:260143
28th IEEE Real-Time Systems Symposium RTSS07