A heuristic for thermal-safe SoC test scheduling
2007 (English)In: IEEE International Test Conference, 2007, IEEE , 2007, 116-125 p.Conference paper (Refereed)
High temperature has become a technological barrier to the testing of high performance systems-on-chip, especially when deep submicron technologies are employed. In order to reduce test time while keeping the temperature of the cores under test within a safe range, thermal-aware test scheduling techniques are required. In this paper, we address the test time minimization problem as how to generate the shortest test schedule such that the temperature limits of individual cores and the limit on the test-bus bandwidth are satisfied. In order to avoid overheating during the test, we partition test sets into shorter test sub-sequences and add cooling periods in between, such that continuously applying a test sub-sequence will not drive the core temperature going beyond the limit. Further more, based on the test partitioning scheme, we interleave the test sub-sequences from different test sets in such a manner that a cooling period reserved for one core is utilized for the test transportation and application of another core. We have proposed a heuristic to minimize the test application time by exploring alternative test partitioning and interleaving schemes with variable length of test sub-sequences and cooling periods. Experimental results have shown the efficiency of the proposed heuristic.
Place, publisher, year, edition, pages
IEEE , 2007. 116-125 p.
, International Test Conference. Proceedings, ISSN 1089-3539
testing, system-on-chip, SOC, thermal-aware, test scheduling, test partitioning, design optimization
IdentifiersURN: urn:nbn:se:liu:diva-39298DOI: 10.1109/TEST.2007.4437573ISI: 000255939900014Local ID: 47832ISBN: 978-1-4244-1127-6ISBN: e-978-1-4244-1128-3OAI: oai:DiVA.org:liu-39298DiVA: diva2:260147
IEEE International Test Conference(ITC 2007), 21-26 October 2007, Santa Clara, CA, USA