Extended STAPL as SJTAG Engine
2007 (English)In: IEEE European Test Symposium,2007, Freiburg, Germany: IEEE Computer Society Press , 2007, 119- p.Conference paper (Refereed)
Integrated Circuits (ICs) and multi-board systems are becoming increasingly complex to test. A key to successful testing is effective standards. Currently, at micro level the Internal JTAG (IJTAG) focuses on the development of a standard for embedded on-chip instruments while at macro level the System JTAG (SJTAG) works on defining a standard for system level test management; mainly connecting the IJTAG standard with the system test manager. In this paper we discuss language requirement for making and handling access between the test manager and embedded instruments. As a base-line we make use of the Standard Test and Programming Language (STAPL). We have identified a number of required extensions that we have implemented in an extended STAPL++ player (interpreter) and language. We have performed initial experiments where we simulated an embedded environment with a PC as test controller running the new player and an FPGA serving as device-under-test.
Place, publisher, year, edition, pages
Freiburg, Germany: IEEE Computer Society Press , 2007. 119- p.
testing, multi-board systems, language requirement, test protocol, standards
IdentifiersURN: urn:nbn:se:liu:diva-39299Local ID: 47833OAI: oai:DiVA.org:liu-39299DiVA: diva2:260148