A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing
2007 (English)In: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems,2007, Krakow, Poland: IEEE Computer Society Press , 2007, 61- p.Conference paper (Refereed)
The increasing cost for System-on-Chip (SOC) testing is mainly due to the huge test data volumes that lead to long test application time and require large automatic test equipment (ATE) memory. Test compression and test sharing have been proposed to reduce the test data volume, while test infrastructure and concurrent test scheduling have been developed to reduce the test application time. In this work we propose an integrated test scheduling and test infrastructure design approach that utilizes both test compression and test sharing as basic mechanisms to reduce test data volumes. In particular, we have developed a heuristic to minimize the test application time, considering different alternatives of test compression and sharing, without violating a given ATE memory constraint. The results from the proposed Tabu Search based heuristic have been validated using benchmark designs and are compared with optimal solutions.
Place, publisher, year, edition, pages
Krakow, Poland: IEEE Computer Society Press , 2007. 61- p.
testing, system-on-chip, memory reduction, test scheduling, test data compression, test sharing, tabu search
IdentifiersURN: urn:nbn:se:liu:diva-39300DOI: 10.1109/DDECS.2007.4295255Local ID: 47834ISBN: 1-4244-1162-9ISBN: 1-4244-1162-9OAI: oai:DiVA.org:liu-39300DiVA: diva2:260149
IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems,2007