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Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
2007 (English)In: Vlsi-Soc: From Systems To Silicon / [ed] Ricardo Reis, Adam Osseiran, Hans-Joerg Pfleiderer, Boston, USA: Springer , 2007, 221-244 p.Chapter in book (Other academic)
Abstract [en]

Testing is used to ensure high quality chip production. High test quality implies the application of high quality test data; however, the technology development has lead to a need of an increasing test data volume to ensure high test quality. The problem is that the test data volume has to fit the limited memory of the ATE (Automatic Test Equipment). In this paper, we propose a test data truncation scheme that for a modular core-based SOC (System-on-Chip) selects test data volume in such a way that the test quality is maximized while the selected test data is guaranteed to met the ATE memory constraint. We define, for each core as well as for the system, a test quality metric that is based on fault coverage, defect probability and number of applied test vectors. The proposed test data truncation scheme selects the appropriate number of test vectors for each individual core based on the test quality metric, and schedules the transportation of the selected test data volume on the Test Access Mechanism such that the system-s test quality is maximized and the test data fits the ATE-s memory. We have implemented the proposed technique and the experimental results, produced at reasonable CPU times, on several ITC-02 benchmarks show that high test quality can be achieved by a careful selection of test data. The results indicate that the test data volume (test application time) can be reduced to about 50% while keeping a high test quality.

Place, publisher, year, edition, pages
Boston, USA: Springer , 2007. 221-244 p.
Series
IFIP International Federation for Information Processing, 240
Keyword [en]
testing, system-on-chip, SOC, test data truncation, test vectors, test access mechanism, TAM
National Category
Computer Science
Identifiers
URN: urn:nbn:se:liu:diva-39302DOI: 10.1007/978-0-387-73661-7Local ID: 47837ISBN: 978-0-387-73660-0 (print)ISBN: 978-0-387-73661-7 (print)OAI: oai:DiVA.org:liu-39302DiVA: diva2:260151
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2013-08-16Bibliographically approved

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Publisher's full textfind book at a swedish library/hitta boken i ett svenskt bibliotek

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Larsson, ErikEdbom, Stina

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  • apa
  • harvard1
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