Predictable Implementation of Real-Time Applications on Multiprocessor Systems on Chip
2008 (English)In: VLSI Design, 2008. VLSID 2008, IEEE Computer Society, 2008, 103-110 p.Conference paper (Refereed)
Worst-case execution time (WCET) analysis and, in general, the predictability of real-time applications implemented on multiprocessor systems has been addressed only in very restrictive and particular contexts. One important aspect that makes the analysis difficult is the estimation of the system-s communication behavior. The traffic on the bus does not solely originate from data transfers due to data dependencies between tasks, but is also affected by memory transfers as result of cache misses. As opposed to the analysis performed for a single processor system, where the cache miss penalty is constant, in a multiprocessor system each cache miss has a variable penalty, depending on the bus contention. This affects the tasks- WCET which, however, is needed in order to perform system scheduling. At the same time, the WCET depends on the system schedule due to the bus interference. In this context, we propose, for the first time, an approach to worst-case execution time analysis and system scheduling for real-time applications implemented on multiprocessor SoC architectures.
Place, publisher, year, edition, pages
IEEE Computer Society, 2008. 103-110 p.
, International Conference on VLSI Design. Proceedings, ISSN 1063-9667
embedded systems, worst-case execution time analysis, WCET, distributed systems, system-on-chip, SOC, scheduling
IdentifiersURN: urn:nbn:se:liu:diva-39303DOI: 10.1109/VLSI.2008.33ISI: 000253939700024Local ID: 47838ISBN: 0-7695-3083-4ISBN: 978-0-7695-3083-3OAI: oai:DiVA.org:liu-39303DiVA: diva2:260152
21st International Conference on VLSI Design (VLSID 2008), 4-8 January 2008, Hyderabad, India