Scheduling and Voltage Scaling for Energy/Reliability Trade-offs in Fault-Tolerant Time-Triggered Embedded Systems
2007 (English)In: 5th Intl. Conf. on Hardware/Software Codesign and System Synthesis CODES+ISSS,2007, Salzburg, Austria: IEEE Computer Society Press , 2007, 233- p.Conference paper (Refereed)
In this paper we present an approach to the scheduling and voltage scaling of low-power fault-tolerant hard real-time applications mapped on distributed heterogeneous embedded systems. Processes and messages are statically scheduled, and we use process re-execution for recovering from multiple transient faults. Addressing simultaneously energy and reliability is especially challenging because lowering the voltage to reduce the energy consumption has been shown to exponentially increase the number of transient faults. In addition, time-redundancy based fault-tolerance techniques such as re-execution and dynamic voltage scaling-based low-power techniques are competing for the slack in the schedules. Our approach decides the voltage levels and start times of processes and the transmission times of messages, such that the transient faults are tolerated, the timing constraints of the application are satisfied and the energy is minimized. We present a constraint logic programming- based approach which is able to find reliable and schedulable implementations within limited energy and hardware resources. The developed algorithms have been evaluated using extensive experiments.
Place, publisher, year, edition, pages
Salzburg, Austria: IEEE Computer Society Press , 2007. 233- p.
embedded systems, fault tolerance, low power, design optimization, reliability, transient faults
IdentifiersURN: urn:nbn:se:liu:diva-39305DOI: 10.1145/1289816.1289873Local ID: 47846ISBN: 978-1-59593-824-4OAI: oai:DiVA.org:liu-39305DiVA: diva2:260154
5th Intl. Conf. on Hardware/Software Codesign and System Synthesis CODES+ISSS,2007