Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns
2008 (English)In: Design, Automation, and Test in Europe DATE 2008,2008, Munich, Germany: IEEE Computer Society Press , 2008, 188- p.Conference paper (Refereed)
The ever-increasing test data volume for core-based system-on-chip (SOC) integrated circuits is resulting in high test times and excessive tester memory requirements. To reduce both test time and test data volume, we propose a technique for test-architecture optimization and test scheduling that is based on core-level expansion of compressed test patterns. For each wrapped embedded core and its decompressor, we show that the test time does not decrease monotonically with the width of test access mechanism (TAM) at the decompressor input. We optimize the wrapper and decompressor designs for each core, as well as the TAM architecture and the test schedule at the SOC level. Experimental results for SOCs crafted from several industrial cores demonstrate that the proposed method leads to significant reduction in test data volume and test time, especially when compared to a method that does not rely on core-level decompression of patterns.
Place, publisher, year, edition, pages
Munich, Germany: IEEE Computer Society Press , 2008. 188- p.
testing, system-on-chip, test-architecture optimization, test scheduling, test patterns, compression, test access mechanism, TAM, SOC
IdentifiersURN: urn:nbn:se:liu:diva-39638DOI: 10.1109/DATE.2008.4484684Local ID: 50430ISBN: 978-3-9810801-3-1ISBN: 978-3-9810801-4-8OAI: oai:DiVA.org:liu-39638DiVA: diva2:260487
Design, Automation, and Test in Europe DATE 2008