An Integrated System-on-Chip Test Framework
2008 (English)In: Design, Automation, and Test in Europe: The Most Influential Papers of 10 Years DATE, Dordrecht, The Netherlands: Springer , 2008, 1, 439-454 p.Chapter in book (Other academic)
In this paper we propose a framework for the testing of system-on-chip (SOC), which includes a set of design algorithms to deal with test scheduling, test access mechanism design, test sets selection, test parallelization, and test resource placement. The approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests, power consumption and test resources. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. Experimental results shows the efficiency and the usefulness of the proposed technique.
Place, publisher, year, edition, pages
Dordrecht, The Netherlands: Springer , 2008, 1. 439-454 p.
testing, system-on-chip, SOC, framework, integrated testing
IdentifiersURN: urn:nbn:se:liu:diva-39641Local ID: 50433ISBN: 978-1-4020-6487-6ISBN: 978-1-4020-6488-3OAI: oai:DiVA.org:liu-39641DiVA: diva2:260490