Parallelization of High-Performance Video Encoding on a Single-Chip Multiprocessor
2007 (English)In: IEEE International Conference on Signal Processing and Communications,2007, IEEE , 2007Conference paper (Refereed)
Although single-chip multiprocessor architectures are available nowadays for embedded computing, programming them with efficiency and productivity has become a significant challenge. This paper studies the multi-level parallelization of video encoding algorithms on a state-of-the-art on-chip multiprocessor. The encoding of H.264/AVC video is chosen as the case to be studied because of its performance demanding and branch-rich features. The final benchmarking result proves that the optimized processing flow can achieve more than 100 operations per cycle in performance which allows a single-chip multiprocessor to encode high resolution video (1920 x 1080) in real-time (30 fps).
Place, publisher, year, edition, pages
IEEE , 2007.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-39866DOI: 10.1109/ICSPC.2007.4728276Local ID: 51550ISBN: 978-1-4244-1235-8ISBN: 978-1-4244-1236-5OAI: oai:DiVA.org:liu-39866DiVA: diva2:260715
IEEE International Conference on Signal Processing and Communications