A Technique for Test Infrastructure Design and Test Scheduling
2000 (English)In: Design and Diagnostic of Electronic Circuits and Systems Workshop DDECS 2000,2000, Smolenice Castle, Slovakia: IEEE Computer Society Press , 2000, 26- p.Conference paper (Refereed)
We propose a technique for test scheduling and design of test bus infrastructure where test application time and test bus length and width are minimized while constraints on power consumption and test resources are considered. Our approach is suitable for repeated use in the design space exploration process due to its low computational cost. For the final design, we use simulated annealing to optimize the solution. Our technique has been implemented and experimental results show the efficiency of our approach.
Place, publisher, year, edition, pages
Smolenice Castle, Slovakia: IEEE Computer Society Press , 2000. 26- p.
testing, simulated annealing, test scheduling, test bus infrastructure
National CategoryComputer Science
IdentifiersURN: urn:nbn:se:liu:diva-40153Local ID: 52446OAI: oai:DiVA.org:liu-40153DiVA: diva2:261002
Design and Diagnostic of Electronic Circuits and Systems Workshop DDECS 2000, 2000 Smolenice Castle, Slovakia