System-on-Chip Test Bus Design and Test Scheduling
2000 (English)In: International Test Synthesis Workshop,2000, 2000Conference paper (Refereed)
We propose a technique for test scheduling and test bus infrastructure design. In our approach, we consider constraints on the power consumption and on the design for test resources, while minimizing the test application time and the test bus length. The technique has a low computational cost which is important when it is used repeatedly in the design space exploration process. For the final design, we use Simulated annealing to optimize the solution. The proposed technique has been been implemented and experimental results show the efficiency of our approach.
Place, publisher, year, edition, pages
testing, test scheduling, test bus infrastructure design, power consumption, simulated annealing
National CategoryComputer Science
IdentifiersURN: urn:nbn:se:liu:diva-40154Local ID: 52447OAI: oai:DiVA.org:liu-40154DiVA: diva2:261003
7th IEEE International Test Synthesis Workshop, March 2000, Santa Barbara, California, USA