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Power optimized partial product reduction interconnect ordering in parallel multipliers
Department of Electronics and Telecommunications Norwegian University of Science and Technology NTNU.
Department of Electronics and Telecommunications Norwegian University of Science and Technology NTNU.
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.ORCID iD: 0000-0003-3470-3911
2007 (English)In: Norchip,2007, Piscataway: IEEE , 2007Conference paper, Published paper (Refereed)
Abstract [en]

When designing the reduction tree of a parallel multiplier, we can exploit a large intrinsic freedom for the interconnection order of partial products. The transition activities vary significantly for different internal partial products. In this work we propose a method for generation of power-efficient parallel multipliers in such a way that its partial products are connected to minimize activity. The reduction tree is designed progressively. A Simulated Annealing optimizer uses power cost numbers from a specially implemented probabilistic gate-level power estimator and selects a power-efficient solution for each stage of the reduction tree. VHDL simulation using ModelSim shows a significant reduction in the overall number of transitions. This reduction ranges from 15% up to 32% compared to randomly generated reduction trees and is achieved without any noticeable area or performance overhead.

Place, publisher, year, edition, pages
Piscataway: IEEE , 2007.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-40573Local ID: 53513OAI: oai:DiVA.org:liu-40573DiVA: diva2:261422
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2015-03-11

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http://www.iet.ntnu.no/projects/cuban/archive/071007.pdf

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Gustafsson, Oscar

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