Bit-Level Optimization of Shift-and-Add Based FIR Filters
2007 (English)In: IEEE International Conference on Electronics, Circuits and Systems,2007, Piscataway, NJ: IEEE , 2007, , 713-716 p.713-716 p.Conference paper (Refereed)
Implementation of FIR filters using shift-and-add multipliers has been an active research area for the last decade. However, almost all algorithms so far has been focused on reducing the number of adders and subtractors, while little effort was put on the bit-level implementation. In this work we propose a method to optimize the number of full adders and half adders required to realize a given number of additions. We present results which show that both area and power consumption can be reduced using the proposed method.
Place, publisher, year, edition, pages
Piscataway, NJ: IEEE , 2007. , 713-716 p.713-716 p.
low power, low complexity, FIR filters, adder depth, multiple-constant multiplication
National CategoryEngineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-40719Local ID: 53985OAI: oai:DiVA.org:liu-40719DiVA: diva2:261568