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Hybrid Parallel Sort on the Cell Processor
FernUniversität in Hagen, Fak. Math. und Informatik, Hagen, Germany.
Linköping University, Department of Computer and Information Science, PELAB - Programming Environment Laboratory. Linköping University, The Institute of Technology.ORCID iD: 0000-0001-5241-0026
Technische Universit¨at Darmstadt, FB Informatik, Darmstadt, Germany.
Technische Universit¨at Darmstadt, FB Informatik, Darmstadt, Germany.
2008 (English)In: 9th Workshop on Parallel Systems and Algorithms (PASA) / [ed] Wolfgang E. Nagel, Rolf Hoffmann, Andreas Koch, Bonn, Germany: Gesellschaft für Informatik, 2008, 107-112 p.Conference paper, Published paper (Refereed)
Abstract [en]

Sorting large data sets has always been an important application, and hence has been one of the benchmark applications on new parallel architectures. We present a parallel sorting algorithm for the Cell processor that combines elements of bitonic sort and merge sort, and reduces the bandwidth to main memory by pipelining. We present runtime results of a partial prototype implementation and simulation results for the complete sorting algorithm, that promise performance advantages over previous implementations.

Place, publisher, year, edition, pages
Bonn, Germany: Gesellschaft für Informatik, 2008. 107-112 p.
Series
GI Lecture Notes in Informatics, 124
Keyword [en]
parallel mergesort, multicore, bandwidth limitation, pipelining, load balancing, on-chip communication network
National Category
Computer Science
Identifiers
URN: urn:nbn:se:liu:diva-42101Local ID: 60495ISBN: 978-3-88579-218-5 (print)OAI: oai:DiVA.org:liu-42101DiVA: diva2:262956
Conference
The 21st Conference on the Architecture of Computing Systems (ARCS),February 26th, 2008 in Dresden, Germany
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2014-10-08Bibliographically approved

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Kessler, Christoph

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CiteExportLink to record
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Citation style
  • apa
  • harvard1
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Output format
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