Hybrid Parallel Sort on the Cell Processor
2008 (English)In: 9th Workshop on Parallel Systems and Algorithms (PASA) / [ed] Wolfgang E. Nagel, Rolf Hoffmann, Andreas Koch, Bonn, Germany: Gesellschaft für Informatik, 2008, 107-112 p.Conference paper (Refereed)
Sorting large data sets has always been an important application, and hence has been one of the benchmark applications on new parallel architectures. We present a parallel sorting algorithm for the Cell processor that combines elements of bitonic sort and merge sort, and reduces the bandwidth to main memory by pipelining. We present runtime results of a partial prototype implementation and simulation results for the complete sorting algorithm, that promise performance advantages over previous implementations.
Place, publisher, year, edition, pages
Bonn, Germany: Gesellschaft für Informatik, 2008. 107-112 p.
, GI Lecture Notes in Informatics, 124
parallel mergesort, multicore, bandwidth limitation, pipelining, load balancing, on-chip communication network
IdentifiersURN: urn:nbn:se:liu:diva-42101Local ID: 60495ISBN: 978-3-88579-218-5OAI: oai:DiVA.org:liu-42101DiVA: diva2:262956
The 21st Conference on the Architecture of Computing Systems (ARCS),February 26th, 2008 in Dresden, Germany