Synthesis of Fault-Tolerant Embedded Systems
2008 (English)In: Design, Automation and Test in Europe, 2008., Munich, Germany: IEEE , 2008, 960-965 p.Conference paper (Refereed)
This work addresses the issue of design optimization for fault-tolerant hard real-time systems. In particular, our focus is on the handling of transient faults using both checkpointing with rollback recovery and active replication. Fault tolerant schedules are generated based on a conditional process graph representation. The formulated system synthesis approaches decide the assignment of fault-tolerance policies to processes, the optimal placement of checkpoints and the mapping of processes to processors, such that multiple transient faults are tolerated, transparency requirements are considered, and the timing constraints of the application are satisfied.
Place, publisher, year, edition, pages
Munich, Germany: IEEE , 2008. 960-965 p.
, Design, Automation, and Test in Europe Conference and Exhibition. Proceedings, ISSN 1530-1591
embedded systems, fault tolerance, scheduling, mapping, policy assignment, transient faults
IdentifiersURN: urn:nbn:se:liu:diva-42253DOI: 10.1109/DATE.2008.4484825ISI: 000257940700165Local ID: 62056ISBN: 978-3-9810801-3-1ISBN: e-978-3-9810801-4-8OAI: oai:DiVA.org:liu-42253DiVA: diva2:263109
Design, Automation and Test in Europe Conference and Exhibition (DATE 2008), 10-14 Mars 2008, Munich, Germany