Power amplifiers for WLAN in 65nm CMOS
2008 (English)Conference paper (Other academic)
This paper describes the design of two power amplifiers (PA) for WLAN 802.11n fabricated in 65nm CMOS technology. Both PAs utilize 3.3V thick-gate oxide (5.2nm) transistors and employ a two-stage differential structure, but the input and interstage matching networks are realized differently. The first PA uses LC matching networks for matching, while the second PA uses on-chip transformers. EVM, output power levels, and spectral masks are obtained for a 72.2Mbit/s, 64-QAM 802.11n OFDM signal.
Place, publisher, year, edition, pages
National CategoryEngineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-42410Local ID: 63780OAI: oai:DiVA.org:liu-42410DiVA: diva2:263267
Swedish System-on-Chip Conference SSoCC, May 5-6, Gnesta, Sweden