Very Low Cost Configurable Hardware Interleaver for 3G Turbo Decoding
2008 (English)In: IEEE Internation Conference on Information and Communication Tech from Theory to Applications, ICTTA,2008, IEEE , 2008, 2314-2318 p.Conference paper (Refereed)
A very low cost hardware interleaver for 3rd Generation Partnership Project (3GPP) turbo coding algorithm is presented. The interleaver is a key component of turbo codes and it is used to minimize the effect of burst errors in the transmission. Using conventional design methods, it consumes a large part of silicon area in the design of turbo encoder and decoder. The presented hardware interleaver architecture utilizes the algorithmic level hardware simplifications as well as the iterative modulo computation to achieve very low cost solution. After doing the hardware multiplexing and optimization the proposed architecture consumes only 1.5 k gates (without pre-computation) and 2.2 k gates (with pre-computation). In both cases the interleaved address is computed every clock cycle except the case of pruning, in which one additional clock cycle is consumed.
Place, publisher, year, edition, pages
IEEE , 2008. 2314-2318 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-42733DOI: 10.1109/ICTTA.2008.4530232Local ID: 68459ISBN: 978-1-4244-1752-0ISBN: 978-1-4244-1751-3OAI: oai:DiVA.org:liu-42733DiVA: diva2:263590
3rd International Conference on Information and Communication Technologies