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Aspects of system-on-chip design for FPGAs
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.ORCID iD: 0000-0002-0111-2384
2008 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

Due to the increasing NRE costs of recent ASICs, the use of FPGAs is expected to continue to increase. While the first FPGAs were limited devices useful mainly for glue logic, todays FPGAs are highly capable devices used in many different application areas including telecommunication, multimedia, medical, and automotive. This means that many VLSI designers need to deal with FPGAs, either as the primary target, or as a prototype platform. The design methodology for an ASIC and FPGA are similar, but if high performance is expected from the FPGA, it is necessary to take FPGA limitations related to memories, data path components, I/O, and routing delays into account early in the design cycle for both FPGA prototyping and FPGA products.

This thesis investigates these limitations through three case studies of important VLSI building blocks. The thesis also discusses how a designer can gain additional information from the FPGA backend flow through custom tools and presents a framework for designing such tools.

The first case study discusses the opportunities and problems when designing both the data path and control path components of a high speed processor in an FPGA. The resulting processor core is a RISC processor with some DSP extensions which has a clock frequency which is significantly higher than the Micro blaze processor which has been specifically developed for Xilinx FPGAs. This case study focuses on the tradeoffs which are necessary to reach this performance in an FPGA.

The second case study describes how a floating point adder and multiplier can be optimized for FPGAs. This is a very important area as the use of floating point arithmetic can significantly reduce the design time of some applications. The solution presented in the thesis outperforms previous academic publications and has a performance similar to commercial offerings.

The third case study presents a packet switched Network-on-Chip (NoC) architecture. While NoCs are not commonly used in FPGA designs today it is expected that they will become an important component in future FPGA designs, especially when prototyping large NoC based ASICs.

Finally, a framework is presented which allows a designer to write custom backend tool by modifying Xilinx XDL files. While the framework is already useful for some tasks, the main reason for including it is to inspire both researchers and developers to look into this area by showing that it is actually quite easy to write such tools.

Place, publisher, year, edition, pages
Linköping: Linköpings universitet , 2008. , 72 p.
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 1376
Series
LiU-TEK-LIC, 45
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-42791Local ID: 68799ISBN: 978-91-7393-848-8 (print)OAI: oai:DiVA.org:liu-42791DiVA: diva2:263648
Presentation
2008-06-13, Sal Glashuset, Linköpings universitet, Linköping, 10:15 (Swedish)
Opponent
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2015-02-18
List of papers
1. High Performance, Low Latency FPGA based Floating Point Adder and Multiplier Units in a Virtex 4
Open this publication in new window or tab >>High Performance, Low Latency FPGA based Floating Point Adder and Multiplier Units in a Virtex 4
2006 (English)In: NORCHIP 2006: The Nordic Microelectronics Event. 2006, 2006, 31-34 p.Conference paper, Published paper (Refereed)
Abstract [en]

Since the invention of FPGAs, the increase in their size and performance has allowed designers to use FPGAs for more complex designs. FPGAs are generally good at bit manipulations and fixed point arithmetics but has a harder time coping with floating point arithmetics. In this paper we describe methods used to construct high performance floating point components in a Virtex-4. We have constructed a floating point adder/subtracter and multiplier which we then used to construct a complex radix-2 butterfly. Our adder/subtracter can operate at a frequency of 361 MHz in a Virtex-4SX35 (speed grade -12)

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-100922 (URN)10.1109/NORCHP.2006.329238 (DOI)9781424407729 (ISBN)
Conference
24th Norchip Conference, 20-21 November 2006, Linkoping, Sweden.
Available from: 2013-11-14 Created: 2013-11-14 Last updated: 2015-02-18
2. An FPGA based Open Source Network-on-chip Architecture
Open this publication in new window or tab >>An FPGA based Open Source Network-on-chip Architecture
2007 (English)In: 17th International Conference on Fileld Programmable Logic and Applications, FPL, Amsterdam, Holland, 2007, IEEE , 2007, 800-803 p.Conference paper, Published paper (Refereed)
Abstract [en]

Networks on chip (NoC) has long been seen as a potential solution to the problems encountered when implementing large digital hardware designs. In this paper we describe an open source FPGA based NoC architecture with low area overhead, high throughput and low latency compared to other published works. The architecture has been optimized for Xilinx FPGAs and the NoC is capable of operating at a frequency of 260 MHz in a Virtex-4 FPGA. We have also developed a bridge so that generic Wishbone bus compatible IP blocks can be connected to the NoC.

Place, publisher, year, edition, pages
IEEE, 2007
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-16560 (URN)10.1109/FPL.2007.4380772 (DOI)978-1-4244-1060-6 (ISBN)
Available from: 2009-02-02 Created: 2009-02-02 Last updated: 2015-02-18Bibliographically approved
3. Thinking outside the flow: Creating customized backend tools for Xilinx based designs
Open this publication in new window or tab >>Thinking outside the flow: Creating customized backend tools for Xilinx based designs
2007 (English)In: 4th annual FPGAworld Conference, Stockholm, 2007, 2007Conference paper, Published paper (Refereed)
Abstract [en]

This paper is intended to serve as an introduction to how to build a customized backend tool for a Xilinx based design flow. A Python based library called PyXDL is presented which allows a user to manipulate XDL files which contain a placed and routed design. Three different tools are presented which uses this library, ranging from a simple resource utilization viewer to a tool which will insert a logic analyzer into an already routed design, thus avoiding a costly complete rerun of the place and route tool.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-16561 (URN)
Available from: 2009-02-02 Created: 2009-02-02 Last updated: 2015-02-18Bibliographically approved
4. A High Performance Microprocessor with DSP Extensions Optimized for the Virtex-4 FPGA
Open this publication in new window or tab >>A High Performance Microprocessor with DSP Extensions Optimized for the Virtex-4 FPGA
2008 (English)In: International Conference on Field Programmable Logic and Applications FLP 2008, Heidelberg, Germany, 2008, 2008, 599-602 p.Conference paper, Published paper (Refereed)
Abstract [en]

As the use of FPGAs increases, the importance of highly optimized processors for FPGAs will increase. In this paper we present the microarchitecture of a soft microprocessor core optimized for the Virtex-4 architecture. The core can operate at 357 MHz, which is significantly faster than Xilinxpsila Microblaze architecture on the same FPGA. At this frequency it is necessary to keep the logic complexity down and this paper shows how this can be done while retaining sufficient functionality for a high performance processor.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-16562 (URN)10.1109/FPL.2008.4630018 (DOI)978-1-4244-1960-9 (ISBN)
Available from: 2009-02-02 Created: 2009-02-02 Last updated: 2015-02-18Bibliographically approved

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