2.6 Gb/s Over a Four-Drop Bus Using an Adaptive 12-Tap DFE
2008 (English)In: ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference, Bristol, UK: IOP Institute of Physics , 2008, 470-473 p.Conference paper (Refereed)
For PC DRAM buses, the number of slots per channel has decreased as data rates have increased. This limits the maximum memory capacity per channel. Signal equalization can be used to increase bit-rates for channels with a large number of slots and offer a cost effective method to solve the memory capacity problem. This paper presents a blind adaptive decision feedback equalizer (DFE) that enables high data-rates with a large number of slots per channel. Measurements at 2.6 Gb/s over a four-drop bus are presented.
Place, publisher, year, edition, pages
Bristol, UK: IOP Institute of Physics , 2008. 470-473 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-43025DOI: 10.1109/ESSCIRC.2008.4681894Local ID: 70859ISBN: 978-1-4244-2362-0 (online)ISBN: 978-1-4244-2361-3 (print)OAI: oai:DiVA.org:liu-43025DiVA: diva2:263882
European Solid-State Circuits Conference,2008