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2.6 Gb/s Over a Four-Drop Bus Using an Adaptive 12-Tap DFE
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
2008 (English)In: ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference, Bristol, UK: IOP Institute of Physics , 2008, 470-473 p.Conference paper, Published paper (Refereed)
Abstract [en]

For PC DRAM buses, the number of slots per channel has decreased as data rates have increased. This limits the maximum memory capacity per channel. Signal equalization can be used to increase bit-rates for channels with a large number of slots and offer a cost effective method to solve the memory capacity problem. This paper presents a blind adaptive decision feedback equalizer (DFE) that enables high data-rates with a large number of slots per channel. Measurements at 2.6 Gb/s over a four-drop bus are presented.  

Place, publisher, year, edition, pages
Bristol, UK: IOP Institute of Physics , 2008. 470-473 p.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-43025DOI: 10.1109/ESSCIRC.2008.4681894Local ID: 70859ISBN: 978-1-4244-2362-0 (print)ISBN: 978-1-4244-2361-3 (print)OAI: oai:DiVA.org:liu-43025DiVA: diva2:263882
Conference
European Solid-State Circuits Conference,2008
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2014-05-15

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Fredriksson, HenrikSvensson, Christer

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