A 2-GHz 7-mW Digital DLL-Based Frequency Multiplier in 90-nm CMOS
2008 (English)In: ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference, Bristol, UK: IOP Institute of Physics , 2008, 86-89 p.Conference paper (Refereed)
This paper presents a low-power low-jitter digital DLL-based frequency multiplier in 90-nm CMOS. In order to reduce the jitter and power consumption due to dithering in the lock condition, digital DLL operates in the open-loop mode after locking. To keep track of any potential phase error introduced by the environmental variations, a compensation mechanism is employed. The proposed frequency multiplier operates at 2-GHz utilizing a 1-V supply. It occupies 0.037 mm2 of active area and dissipates 7-mW power at 2-GHz. The measured peak-to-peak and rms clock jitter at the output of the frequency multiplier are 9.5 ps and 1.6 ps, respectively.
Place, publisher, year, edition, pages
Bristol, UK: IOP Institute of Physics , 2008. 86-89 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-43026DOI: 10.1109/ESSCIRC.2008.4681798Local ID: 70879ISBN: 978-1-4244-2362-0 (online)ISBN: 978-1-4244-2361-3 (print)OAI: oai:DiVA.org:liu-43026DiVA: diva2:263883
European Solid-State Circuits Conference,2008