ADC on-Chip Dynamic Test by PWM Technique
2008 (English)In: International Conference on Signals and Electronic Systems, IEEE , 2008, 15-18 p.Conference paper (Refereed)
This paper investigates the feasibility of pulse width modulation technique (PWM) for dynamic test of ADCs used for high speed applications. The requirements and limitations of digital PWM signal to noise ratio (SNR) are discussed in terms of pulse-width resolution corresponding to the choice of the carrier- and clock frequency of a pulse-width generator. The PWM SNR response is measured by FFT using coherent sampling for different PWM resolution. Low-pas filtering removing high frequency PWM components is introduced as well to improve PWM SNR and prevent intermodulation effects, which tend to hamper the harmonic distortion test (HD). As an example a 4-bit first-order SigmaDelta ADC under dynamic test is simulated and the requirements for PWM resolution with respect to SNR and HD measurements are identified.
Place, publisher, year, edition, pages
IEEE , 2008. 15-18 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-43029DOI: 10.1109/ICSES.2008.4673345Local ID: 70959ISBN: 78-83-88309-47-2OAI: oai:DiVA.org:liu-43029DiVA: diva2:263886
International Conference on Signals and Electronic Systems, ICSES '08, 14-17 Sept, Krakow, Poland