liu.seSearch for publications in DiVA
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Flexible wireless receivers: on-chip testing techniques and design for test
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
2008 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

In recent years the interest in the design of low cost multistandard mobile devices has gone from technical aspiration to commercial essential. Usually, the emerging wireless applications prompt the conception of new wireless standards. The end user wants to access voice, data, and streaming media from single wireless terminal. In RF perspective, these standards differ in frequency band, sensiti vity, data rate, bandwidth, and modulation type. Therefore, a reconfigurable multistandard radio receiver covering most of the cellular, WLAN and short range standards (800MHz-6GHz band) is required. To keep the cost low, high level of integration becomes a necessity for multistandard radio.

Recently, due to aggressive CMOS scaling ƒT of the transistors has reached the value of hundred of GHz. Moreover, CMOS technology is best suited for monolithic integration, so it seems to be the future choice for the realization of such a reconfigurable multistandard receiver. In this thesis, a multiband sampling radio receiver front-end with test circuitry (Off) implemented in 0.13μm CMOS is presented, which is one step ahead in this direction.

In modem radio transceivers, the estimated cost of testing is a significant portion of manufacturing cost and is escalating with every new generation of RF transceivers. In order to reduce the test cost it is important to identify the faulty circuits very early in the design flow even before packaging. In this thesis, two onchip testing techniques to reduce the test time and cost are presented. The first addresses an offset loopback test for integrated RF transceivers which are not suitable for direct loopback. The other is a new technique for symbol error rate test (SER) that is better in sensitivity and test time compared to traditional SER test.

The down side of CMOS scaling is the increase in parameter variability due to process variations and mismatch. Both the test circuitry (Off) and circuit under test (CUT) are affected by these variations. In order to compensate the impact of large process variations on Off circuitry, a new calibration scheme using DC on-chip measurements supported by Artificial Neural Networks (ANN) as a statistical regression method is presented.

Place, publisher, year, edition, pages
Linköping: Linköpings universitet , 2008. , 96 p.
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 1378
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-43570Local ID: 74243ISBN: 978-91-7393-816-7 (print)OAI: oai:DiVA.org:liu-43570DiVA: diva2:264430
Presentation
2008-09-09, Glashuset, Linköpings Universitet, Linköping, 00:00 (Swedish)
Opponent
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2013-11-22
List of papers
1. Multiband RF-Sampling Receiver Front-End with On-Chip Testability in 0.13μm CMOS
Open this publication in new window or tab >>Multiband RF-Sampling Receiver Front-End with On-Chip Testability in 0.13μm CMOS
2009 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 61, no 2, 115-127 p.Article in journal (Refereed) Published
Abstract [en]

In this paper a flexible RF-sampling front-end primarily intended for WLAN standards operating in the 2.4 GHz and 5–6 GHz bands is presented. The circuit is implemented with on-chip Design for Test (DfT) features in 0.13 μm CMOS process. The front-end consists of a wideband LNA, a sampling IQ down-converter implemented as switched-capacitor decimation filter, test attenuator (TA), and RF detectors. The architecture is generic and scalable in frequency. It can operate at a sampling frequency up to 3 GHz and RF carrier up to 6 GHz with 29 subsampling. The selectable decimation factor of 8 or 16 makes the A/D conversion feasible. The frequency response, linearity, and NF of the whole frontend have been measured. The power consumption of complete RF front-end is 176 mW. The on-chip DfT features are helpful in reduction of overall test cost and time in volume production. The measurement results show the feasibility of DfT approach for multiband radio receiver design using standard CMOS process.

Place, publisher, year, edition, pages
Springer Link, 2009
Keyword
DfT, Sampling receiver, Wideband RF front-end, Wideband LNA, Multiband receiver, Multi-standard receiver
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-18195 (URN)10.1007/s10470-009-9286-x (DOI)
Available from: 2009-05-11 Created: 2009-05-11 Last updated: 2017-12-13Bibliographically approved
2. Boosting SER Test for RF Transceivers by Simple DSP Technique
Open this publication in new window or tab >>Boosting SER Test for RF Transceivers by Simple DSP Technique
2007 (English)In: DATE '07 Design, Automation & Test in Europe Conference & Exhibition, 2007., IEEE , 2007, 1-6 p.Conference paper, Published paper (Refereed)
Abstract [en]

The paper presents a new technique of symbol error rate test (SER) for RF transceivers. A simple DSP algorithm implemented at the receiver baseband is introduced in terms of constellation correction, which is usually used to compensate for IQ imbalance. The test is oriented at detection of impairments in gain and noise figure in a transceiver frontend. The proposed approach is shown to enhance the sensitivity of a traditional SER test to the limits of its counterpart, the error vector magnitude (EVM) test. Its advantage over EVM is in simple implementation, lower DSP overhead and the ability of achieving a larger dynamic range of the test response. Also the test time is saved compared to a traditional SER test. The technique is validated by a simulation model of a Wi-Fi transceiver implemented in MatlabTM.

Place, publisher, year, edition, pages
IEEE, 2007
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-18197 (URN)10.1109/DATE.2007.364680 (DOI)978-3-9810801-2-4 (ISBN)
Conference
IEEE Design Automation and Test in Europe Conference (DATE), Acropolis, Nice, France, 16-20 April
Available from: 2009-05-11 Created: 2009-05-11 Last updated: 2013-11-22Bibliographically approved
3. Offset Loopback Test For IC RF Transceivers
Open this publication in new window or tab >>Offset Loopback Test For IC RF Transceivers
2006 (English)In: Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006., Lodz, Poland: Dpt of Microelectronics and Computer Science, Technical University of Lodz , 2006, 583-586 p.Conference paper, Published paper (Refereed)
Abstract [en]

In this paper we develop an offset loopback test setup for integrated RF transceivers (TRx's). Basically, addressed are architectures, which are not suitable for direct loopback test such as FDD transceivers or TDD transceivers where the transmitter (Tx) and receiver (Rx) share one frequency synthesizer (called VCO modulating TRx's). The technique makes use of an extra mixer put on chip to compensate for the incompatibility of the Tx and Rx, i.e. to compensate for a difference between the transmit- and the receive frequency, and/or to introduce a baseband signal needed for test. We discuss the problem in terms of system-level models, which are implemented and verified in Matlabtrade

Place, publisher, year, edition, pages
Lodz, Poland: Dpt of Microelectronics and Computer Science, Technical University of Lodz, 2006
Keyword
RF test, DfT, radio transceivers, RF-CMOS design
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-34570 (URN)10.1109/MIXDES.2006.1706647 (DOI)21895 (Local ID)83-922632-2-7 (ISBN)21895 (Archive number)21895 (OAI)
Conference
IEEE Mixed Design of Integrated Circuits and Systems Conference (MIXDES). Gdynia, Poland. 22-24 June 2006.
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2013-11-22
4. CMOS blocks for on-chip RF test
Open this publication in new window or tab >>CMOS blocks for on-chip RF test
2006 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 49, no 2, 151-150 p.Article in journal (Refereed) Published
Abstract [en]

In this paper we present two designs of CMOS blocks suitable for integration with RF frontend blocks for test purposes. Those are a programmable RF test attenuator and a reconfigurable low noise amplifier (LNA), optimized with respect to their function and location in the circuit. We discuss their performances in terms of the test- and normal operation mode. The presented application model aims at a transceiver under loopback test with enhanced controllability and detectability. The circuits are designed for 0.35μm CMOS process. Simulation results of the receiver frontend operating in 2.4 GHz band are presented showing tradeoffs between the performance and test functionality.

Place, publisher, year, edition, pages
Springer Link, 2006
Keyword
RF test, Loopback test, DfT, Radio transceivers, RF-CMOS design, RF frontend
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-18199 (URN)10.1007/s10470-006-9615-2 (DOI)
Available from: 2009-05-11 Created: 2009-05-11 Last updated: 2017-12-13Bibliographically approved
5. CMOS RF/DC Voltage Detector for on-Chip Test
Open this publication in new window or tab >>CMOS RF/DC Voltage Detector for on-Chip Test
2006 (English)In: IEEE Multitopic Conference, 2006. INMIC '06., Islamabad: M. Ali Jinnah University, Islamabad, Pakistan , 2006, 472-476 p.Conference paper, Published paper (Refereed)
Abstract [en]

In this paper we present a framework for RF testing of a radio front-end using CMOS RF/DC voltage detectors connected between RF nodes and a DC test bus. The detector is designed and implemented in 0.13mum CMOS process and it achieves high input impedance, low power, small area and wide dynamic range. Measurement results show that internal RF nodes can be accessed without significantly degrading the chip performance. A verification procedure using an extra DC bus is proposed to verify that due to process variations all detectors are within an acceptable performance limit.

Place, publisher, year, edition, pages
Islamabad: M. Ali Jinnah University, Islamabad, Pakistan, 2006
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-36824 (URN)10.1109/INMIC.2006.358213 (DOI)32693 (Local ID)1-4244-0795-8 (ISBN)32693 (Archive number)32693 (OAI)
Conference
IEEE Multitopic Conference, 2006. INMIC '06. Islamabad, Pakistan, December 23-24. 2006.
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2013-11-22
6. On-chip calibration of RF detectors by DC stimuli and artificial neural networks
Open this publication in new window or tab >>On-chip calibration of RF detectors by DC stimuli and artificial neural networks
2008 (English)In: Proceedings of 2008 IEEE Radio Frequency Integrated Circuits Symposium, Piscataway, N.J, USA: IEEE , 2008, 571-574 p.Conference paper, Published paper (Refereed)
Abstract [en]

In the nanometer regime, especially the RF and analog circuits exhibit wide parameter variability, and consequently every chip produced needs to be tested. On-chip design for testability (DfT) features, which are meant to reduce test time and cost also suffer from parameter variability. Therefore, RF calibration of all on-chip test structures is mandatory. In this paper, artificial neural networks (ANN) are employed as multivariate regression technique to architect a general RF calibration scheme using DC- instead of RF stimuli. This relaxes the routing requirements on a chip for GHz test signals along with the reduction in test time and cost. The RF detector, a key element of a radio front-end DfT circuitry, designed in 65 nm CMOS is used to demonstrate the calibration scheme.

Place, publisher, year, edition, pages
Piscataway, N.J, USA: IEEE, 2008
Series
IEEE Radio Frequency Integrated Circuits Symposium. Digest of Papers, ISSN 1529-2517
Keyword
ANN application, On-chip RF detector, RF BIST, RF DfT, RF calibration, RF testing
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-18202 (URN)10.1109/RFIC.2008.4561502 (DOI)978-1-4244-1808-4 (ISBN)978-1-4244-1809-1 (ISBN)
Conference
IEEE Radio Frequency Integrated Circuits Symposium, Atlanta, GA, USA, June 15-17 2008
Available from: 2009-05-11 Created: 2009-05-11 Last updated: 2014-03-25Bibliographically approved

Open Access in DiVA

No full text

Authority records BETA

Rashad, Ramzan

Search in DiVA

By author/editor
Rashad, Ramzan
By organisation
Electronic DevicesThe Institute of Technology
Engineering and Technology

Search outside of DiVA

GoogleGoogle Scholar

isbn
urn-nbn

Altmetric score

isbn
urn-nbn
Total: 149 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf