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Optimized On-Chip Pipelining of Memory-Intensive Computations on the Cell BE
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, PELAB - Programming Environment Laboratory.ORCID iD: 0000-0001-5241-0026
Dept. of Mathematics and Computer Science FernUniversität in Hagen, Germany.
2008 (English)In: MCC-2008 First Swedish Workshop on Multicore Computing,2008, Ronneby: Blekinge Institute of Technology , 2008, 50-59 p.Conference paper (Refereed)
Abstract [en]

Multiprocessors-on-chip, such as the Cell BE processor, regularly suffer from restricted bandwidth to off-chip main memory. We propose to reduce memory bandwidth requirements, and thus increase performance, by expressing our application as a task graph, by running dependent tasks concurrently and by pipelining results directly from task to task where possible, instead of buffering in off-chip memory. To maximize bandwidth savings and balance load simultaneously, we solve a mapping problem of tasks to SPEs on the Cell BE. We present three approaches: an integer linear programming formulation that allows to compute Pareto-optimal mappings for smaller task graphs, general heuristics, and a problem specific approximation algorithm. We validate the mappings for dataparallel computations and sorting.

Place, publisher, year, edition, pages
Ronneby: Blekinge Institute of Technology , 2008. 50-59 p.
Keyword [en]
Parallel computing, multicore processor, computer architecture, algorithm engineering, parallel sorting, integer linear programming, approximation algorithm, compiler technology
National Category
Computer Science
URN: urn:nbn:se:liu:diva-43704Local ID: 74569OAI: diva2:264564
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2014-10-08

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