Optimized On-Chip Pipelining of Memory-Intensive Computations on the Cell BE
2008 (English)In: MCC-2008 First Swedish Workshop on Multicore Computing,2008, Ronneby: Blekinge Institute of Technology , 2008, 50-59 p.Conference paper (Refereed)
Multiprocessors-on-chip, such as the Cell BE processor,
regularly suffer from restricted bandwidth to off-chip main
memory. We propose to reduce memory bandwidth requirements,
and thus increase performance, by expressing our
application as a task graph, by running dependent tasks
concurrently and by pipelining results directly from task to
task where possible, instead of buffering in off-chip memory.
To maximize bandwidth savings and balance load simultaneously, we solve a mapping problem of tasks to SPEs on the Cell BE.
We present three approaches: an integer linear programming formulation that allows to compute Pareto-optimal
mappings for smaller task graphs, general heuristics,
and a problem specific approximation algorithm.
We validate the mappings for dataparallel computations and
Place, publisher, year, edition, pages
Ronneby: Blekinge Institute of Technology , 2008. 50-59 p.
Parallel computing, multicore processor, computer architecture, algorithm engineering, parallel sorting, integer linear programming, approximation algorithm, compiler technology
IdentifiersURN: urn:nbn:se:liu:diva-43704Local ID: 74569OAI: oai:DiVA.org:liu-43704DiVA: diva2:264564