Optimal integrated code generation for clustered VLIW architectures
2002 (English)In: joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems LCTES-SCOPES02,2002, New York, USA: ACM , 2002, 102- p.Conference paper (Refereed)
In contrast to standard compilers, generating code for DSPs can afford spending considerable resources in time and space on optimizations. Generating efficient code for irregular architectures requires an integrated method that optimizes simultaneously for instruction selection, instruction scheduling, and register allocation.We describe a method for fully integrated optimal code generation based on dynamic programming. We introduce the concept of residence classes and space profiles, which allows us to describe and optimize for irregular register and memory structures. In order to obtain a retargetable framework we introduce a structured architecture description language, ADML, which is based on XML. We implemented a prototype of such a retargetable system for optimal code generation. Results for variants of the TI C62x show that our method can produce optimal solutions to small but nontrivial problem instances with a reasonable amount of time and space.
Place, publisher, year, edition, pages
New York, USA: ACM , 2002. 102- p.
compiler technology, integrated code generation, dynamic programming, clustered VLIW processor, computer architecture
IdentifiersURN: urn:nbn:se:liu:diva-43708DOI: 10.1145/513829.513849Local ID: 74576OAI: oai:DiVA.org:liu-43708DiVA: diva2:264568