Core-Level Expansion of Compressed Test Patterns
2008 (English)In: Proceedings of the Asian Test Symposium, Sapporo, JAPAN: IEEE Computer Society , 2008, 277-282 p.Conference paper (Refereed)
The increasing test-data volumes needed for the testing of system-on-chip (SOC) integrated circuits lead to long test-application times and high tester memory requirements. Efficient test planning and test-data compression are therefore needed. We present an analysis to highlight the fact that the impact of a test-data compression technique on test time and compression ratio are method-dependant as well as TAM-width dependant. This implies that for a given set of compression schemes, there is no compression scheme that is the optimal with respect to test time reduction and test-data compression at all TAM widths. We therefore propose a technique where we integrate core wrapper design, test architecture design and test scheduling with test-data compression technique selection for each core in order to minimize the SOC test-application time and the test-data volume. Experimental results for several SOCs crafted from industrial cores demonstrate that the proposed method leads to significant reduction in test-data volume and test time.
Place, publisher, year, edition, pages
Sapporo, JAPAN: IEEE Computer Society , 2008. 277-282 p.
integrated circuits, system-on-chip, testing, test-data compression, memory requirements, wrapper design, test-application time
IdentifiersURN: urn:nbn:se:liu:diva-43976DOI: 10.1109/ATS.2008.71Local ID: 75283ISBN: 978-0-7695-3396-4OAI: oai:DiVA.org:liu-43976DiVA: diva2:264837
17th Asian Test Symposium ATS,2008