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Simulation-Driven Thermal-Safe Test Time Minimization for System-on-Chip
Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
2008 (English)In: Asian Test Symposium, 2008. ATS '08, IEEE Computer Society, 2008, 283-288 p.Conference paper, Published paper (Refereed)
Abstract [en]

  Thermal safety has become a major challenge to the testing of systems-on-chip with deep sub-micron technologies. In order to avoid overheating the devices under test while reducing test application times, new techniques are needed. In this paper, we propose a test scheduling technique to minimize the test application time such that the temperatures of individual cores are kept below a given limit. The proposed approach takes into account thermal influences between cores, and thus accurate temperature evolution information of all cores in a system-on-chip is needed for the test scheduling. In order to avoid overheating, we have employed a thermal simulation driven scheduling algorithm, in which instantaneous thermal simulation results are used to guide the partitioning of test sets into test sub-sequences and to determine cooling periods inserted between the partitions. Furthermore, the partitioned test sets for different cores are interleaved such that a cooling period reserved for one core can be utilized for the test-data transportations and test applications for other cores. Experimental results have shown that by using the proposed technique, the test application time is minimized and the temperatures of cores under test are kept below the temperature limit during the entire test process.

Place, publisher, year, edition, pages
IEEE Computer Society, 2008. 283-288 p.
Series
Asian Test Symposium. Proceedings, ISSN 1081-7735
Keyword [en]
systems-on-chip, thermal safety, testing, deep sub-micron, thermal influences, test scheduling, cooling period
National Category
Computer Science
Identifiers
URN: urn:nbn:se:liu:diva-43977DOI: 10.1109/ATS.2008.79ISI: 000264408100055Local ID: 75284ISBN: 978-0-7695-3396-4 (print)OAI: oai:DiVA.org:liu-43977DiVA: diva2:264838
Conference
17th Asian Test Symposium (ATS 08)/9th Workshop on RTL and High Level Testing (WRTLT 08), 24-27 November 2008, Sapporo, Japan
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2013-06-27Bibliographically approved

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He, ZhiyuanPeng, ZeboEles, Petru Ion

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Citation style
  • apa
  • harvard1
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