SOC Test Optimization with Compression-Technique Selection
2008 (English)In: Proceedings - International Test Conference, IEEE , 2008, 1- p.Conference paper (Other academic)
The increasing test-data volumes needed for the testing of system-on-chip (SOC) lead to long test times and high memory requirements. We present an analysis to highlight the fact that the impact of a test-data compression technique on test time and compression ratio are method-dependant as well as TAM-width dependant. Therefore, we propose a technique where compression-technique selection is integrated with core wrapper design, test architecture design, and test scheduling to minimize the SOC test time and the test-data volume.
Place, publisher, year, edition, pages
IEEE , 2008. 1- p.
systems-on-chip, testing, compression
National CategoryComputer Science
IdentifiersURN: urn:nbn:se:liu:diva-43982DOI: 10.1109/TEST.2008.4700685Local ID: 75304ISBN: 978-1-4244-2403-0 (online)ISBN: 978-1-4244-2402-3 (print)OAI: oai:DiVA.org:liu-43982DiVA: diva2:264843
A Workshop in Conjunction with the International Test Conference,2008