Architecture-aware design of a decimation filter based on a dual wordlength multiply-accumulate unit
2008 (English)In: Conference Record - Asilomar Conference on Signals, Systems and Computers, Piscataway, NJ: IEEE , 2008, 1897-1901 p.Conference paper (Refereed)
In this work we present the design and implementation of a decimation filter for an audio range AE-modulator. The architecture is based on a dual wordlength multiply-accumulate (MAC) unit to handle the reduced wordlength of the input. Each stage is composed of FIR filters which are mapped to the MAC unit. The design trade-offs and decisions for co-design of architecture and filters are discussed.
Place, publisher, year, edition, pages
Piscataway, NJ: IEEE , 2008. 1897-1901 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-44136DOI: 10.1109/ACSSC.2008.5074758ISI: 000274551001145Local ID: 75781ISBN: 978-1-4244-2940-0 (print)ISBN: 978-1-4244-2941-7 (online)OAI: oai:DiVA.org:liu-44136DiVA: diva2:264997
2008 42nd Asilomar Conference on Signals, Systems and Computers