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A 2.4-GHz RF sampling receiver front-end in 0.18-μm CMOS
Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
Wavebreaker AB, Norrköping, Sweden.
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2005 (English)In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 40, no 6, 1265-1277 p.Article in journal (Refereed) Published
Abstract [en]

This paper presents an integrable RF sampling receiver front-end architecture, based on a switched-capacitor (SC) RF sampling downconversion (RFSD) filter, for WLAN applications in a 2.4-GHz band. The RFSD filter test chip is fabricated in a 0.18-μm CMOS technology and the measurement results show a successful realization of RF sampling, quadrature downconversion, tunable anti-alias filtering, downconversion to baseband, and decimation of the sampling rate. By changing the input sampling rate, the RFSD filter can be tuned to different RF channels. A maximum input sampling rate of 1072 MS/s has been achieved. A single-phase clock is used for the quadrature downconversion and the bandpass operation is realized by a 23-tap FIR filter. The RFSD filter has an IIP3 of +5.5 dBm, a gain of -1 dB, and more than 17 dB rejection of alias bands. The measured image rejection is 59 dB and the sampling clock jitter is 0.64 ps. The test chip consumes 47 mW in the analog part and 40 mW in the digital part. It occupies an area of 1 mm2.

Place, publisher, year, edition, pages
2005. Vol. 40, no 6, 1265-1277 p.
Keyword [en]
Bandpass filters, CMOS analog integrated circuits, Mixers, Radio receivers, Sample and hold circuits, Switched-capacitor filters
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-45438DOI: 10.1109/JSSC.2005.848027OAI: oai:DiVA.org:liu-45438DiVA: diva2:266334
Available from: 2009-10-11 Created: 2009-10-11 Last updated: 2017-12-13
In thesis
1. Direct RF sampling receivers for wireless systems in CMOS technology
Open this publication in new window or tab >>Direct RF sampling receivers for wireless systems in CMOS technology
2004 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The fast development of wireless communication systems asks for more flexible and more cost-effective radio architectures. A long term goal is a software defined radio, where communication standards are chosen by reconfiguration of hardware. Direct analog-to-digital conversion of the radio frequency (RF) signal is considered unrealistic due to too high requirements on the analog-to-digital converter. This motivates a need for a highly flexible analog front-end that can be fully integrated in a low cost complementary metal-oxide-semiconductor (CMOS) technology.

This thesis exploits the possibility to utilize switched-capacitor (SC) technique for front-end sampling, downconversion, filtering, and decimation. As a result, a new integrable radio receiver front-end architecture is proposed, based on an RF sampling downconversion (RFSD) filter as a discrete-time multi-functional block in SC technique. The front-end architecture is intended for wireless local area network (WLAN) applications in the 2.4 GHz frequency band. A test chip of the RFSD filter has been fabricated in a 0.18-μm CMOS technology and the measurement results show a successful realization of RF sampling, quadrature downconversion, tunable bandpass filtering, downconversion to baseband, and decimation of the sampling rate. The RFSD filter full functionality has been achieved for input sampling rates up to 1 072 MS/s. By changing the input sampling rate, the RFSD filter can be tuned to different RF channels and possibly different bands.

A MOS switch linearization method for a track-and-hold (T/H) circuit is also described in the thesis. This method has been verified with a test chip in a 0.35-μm CMOS technology. The test chip measurement results demonstrate about 5 dB lower harmonic distortion in comparison to an ordinary T/H circuit. Based on the proposed linearization method, a down-conversion sampling mixer has been designed in a 0.35-μm CMOS process. lt has an input-referred third-order intercept point of +22 dBm for a 1.6 GHz input signal, measured at a sampling rate of 1.55 GS/s. The downconversion sampling mixer noise properties are investigated by a noise analysis. The noise analysis is validated by measurement results, which show that the jitter-induced noise is critical for low sampling rates. The downconversion sampling mixer is also proved to be applicable for WCDMA and DECT wireless communication standards in a wideband low intermediate frequency receiver architecture.

To sum up, the presented CMOS sampling receiver front-end is suitable to realize a flexible and highly integrable low cost radio architecture.

Place, publisher, year, edition, pages
Linköping: Linköpings universitet, 2004. 62 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 881
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-22634 (URN)1917 (Local ID)9173739650 (ISBN)1917 (Archive number)1917 (OAI)
Public defence
2004-07-01, Sal Visionen, Linköping Universitet, Linköping, 13:15 (Swedish)
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2017-12-15

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Jakonis, DariusFolkesson, KalleDabrowski, JerzySvensson, Christer

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