Optimal integrated code generation for VLIW architectures
2006 (English)In: Concurrency and Computation, ISSN 1532-0626, Vol. 18, no 11, 1353-1390 p.Article in journal (Refereed) Published
We present a dynamic programming method for optimal integrated code generation for basic blocks that minimizes execution time. It can be applied to single-issue pipelined processors, in-order-issue superscalar processors, VLIW architectures with a single homogeneous register set, and clustered VLIW architectures with multiple register sets. For the case of a single register set, our method simultaneously copes with instruction selection, instruction scheduling, and register allocation. For clustered VLIW architectures, we also integrate the optimal partitioning of instructions, allocation of registers for temporary variables, and scheduling of data transfer operations between clusters. Our method is implemented in the prototype of a retargetable code generation framework for digital signal processors (DSPs), called OPTIMIST. We present results for the processors ARM9E, TI C62x, and a single-cluster variant of C62x. Our results show that the method can produce optimal solutions for small and (in the case of a single register set) medium-sized problem instances with a reasonable amount of time and space. For larger problem instances, our method can be seamlessly changed into a heuristic. Copyright (c) 2006 John Wiley & Sons, Ltd.
Place, publisher, year, edition, pages
2006. Vol. 18, no 11, 1353-1390 p.
instruction-level parallelism, integrated code generation, dynamic programming, instruction scheduling, instruction selection, clustered VLIW architecture, data partitioning
National CategoryEngineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-45996DOI: 10.1002/cpe.1012OAI: oai:DiVA.org:liu-45996DiVA: diva2:266892