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Scheduling with bus access optimization for distributed embedded systems
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
IEEE, Department of Electrical and Computer Engineering and Computer Science, University of Cincinnati, Cincinnati, OH 45221, United States.
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
2000 (English)In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 8, no 5, 472-491 p.Article in journal (Refereed) Published
Abstract [en]

In this paper, we concentrate on aspects related to the synthesis of distributed embedded systems consisting of programmable processors and application-specific hardware components. The approach is based on an abstract graph representation that captures, at process level, both dataflow and the flow of control. Our goal is to derive a worst case delay by which the system completes execution, such that this delay is as small as possible, to generate a logically and temporally deterministic schedule, and to optimize parameters of the communication protocol such that this delay is guaranteed. We have further investigated the impact of particular communication infrastructures and protocols on the overall performance and, specially, how the requirements of such an infrastructure have to be considered for process and communication scheduling. Not only do particularities of the underlying architecture have to be considered during scheduling but also the parameters of the communication protocol should be adapted to fit the particular embedded application. The optimization algorithm, which implies both process scheduling and optimization of the parameters related to the communication protocol, generates an efficient bus access scheme as well as the schedule tables for activation of processes and communications.

Place, publisher, year, edition, pages
2000. Vol. 8, no 5, 472-491 p.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-47573DOI: 10.1109/92.894152OAI: oai:DiVA.org:liu-47573DiVA: diva2:268469
Available from: 2009-10-11 Created: 2009-10-11 Last updated: 2017-12-13

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Eles, Petru IonPop, PaulPeng, Zebo

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